#ifndef _DT_BINDINGS_CLOCK_ROCKCHIP_RK3128_H
#define _DT_BINDINGS_CLOCK_ROCKCHIP_RK3128_H

#include "rockchip.h"

/* pll id */
#define RK3128_APLL_ID		0
#define RK3128_DPLL_ID		1
#define RK3128_CPLL_ID		2
#define RK3128_GPLL_ID		3
#define RK3128_END_PLL_ID	4

/* reset id */
#define RK3128_RST_CORE0_PO		0
#define RK3128_RST_CORE1_PO		1
#define RK3128_RST_CORE2_PO		2
#define RK3128_RST_CORE3_PO		3
#define RK3128_RST_CORE0		4
#define RK3128_RST_CORE1		5
#define RK3128_RST_CORE2		6
#define RK3128_RST_CORE3		7
#define RK3128_RST_CORE0_DBG		8
#define RK3128_RST_CORE1_DBG		9
#define RK3128_RST_CORE2_DBG		10
#define RK3128_RST_CORE3_DBG		11
#define RK3128_RST_TOPDBG		12
#define RK3128_RST_ACLK_CORE		13
#define RK3128_RST_STRC_SYS_A		14
#define RK3128_RST_L2C			15

#define RK3128_RST_1RES0		16
#define RK3128_RST_1RES1		17
#define RK3128_RST_CPUSYS_H		18
#define RK3128_RST_AHB2APB_H		19
#define RK3128_RST_SPDIF		20
#define RK3128_RST_INTMEM		21
#define RK3128_RST_ROM			22
#define RK3128_RST_PERI_NIU		23
#define RK3128_RST_I2S_2CH			24
#define RK3128_RST_I2S_8CH			25
#define RK3128_RST_GPU_PVTM			26
#define RK3128_RST_FUNC_PVTM			27
#define RK3128_RST_1RES12		28
#define RK3128_RST_CORE_PVTM		29
#define RK3128_RST_EFUSE_P		30
#define RK3128_RST_ACODEC_P		31

#define RK3128_RST_GPIO0		32
#define RK3128_RST_GPIO1		33
#define RK3128_RST_GPIO2		34
#define RK3128_RST_GPIO3		35
#define RK3128_RST_MIPIPHY		36
#define RK3128_RST_2RES5		37
#define RK3128_RST_2RES6		38
#define RK3128_RST_UART0		39
#define RK3128_RST_UART1		40
#define RK3128_RST_UART2		41
#define RK3128_RST_2RES10		42
#define RK3128_RST_I2C0			43
#define RK3128_RST_I2C1			44
#define RK3128_RST_I2C2			45
#define RK3128_RST_I2C3			46
#define RK3128_RST_SFC			47

#define RK3128_RST_PWM0			48
#define RK3128_RST_3RES1		49
#define RK3128_RST_DAP_P			50
#define RK3128_RST_DAP			51
#define RK3128_RST_DAP_SYS		52
#define RK3128_RST_CRYPTO		53
#define RK3128_RST_3RES6		54
#define RK3128_RST_GRF			55
#define RK3128_RST_GMAC		56
#define RK3128_RST_PERIPHSYS_A		57
#define RK3128_RST_PERIPHSYS_H		58
#define RK3128_RST_PERIPHSYS_P		59
#define RK3128_RST_SMART_CARD		60
#define RK3128_RST_CPU_PERI		61
#define RK3128_RST_EMEM_PERI		62
#define RK3128_RST_USB_PERI		63

#define RK3128_RST_DMA2			64
#define RK3128_RST_4RES1		65
#define RK3128_RST_4RES2			66
#define RK3128_RST_GPS		67
#define RK3128_RST_NANDC		68
#define RK3128_RST_USBOTG0		69
#define RK3128_RST_4RES6		70
#define RK3128_RST_OTGC0		71
#define RK3128_RST_USBOTG1		72
#define RK3128_RST_4RES9		73
#define RK3128_RST_OTGC1		74
#define RK3128_RST_4RES11		75
#define RK3128_RST_4RES12		76
#define RK3128_RST_4RES13		77
#define RK3128_RST_4RES14		78
#define RK3128_RST_DDRMSCH		79

#define RK3128_RST_5RES0		80
#define RK3128_RST_MMC0			81
#define RK3128_RST_SDIO			82
#define RK3128_RST_EMMC			83
#define RK3128_RST_SPI0			84
#define RK3128_RST_5RES5		85
#define RK3128_RST_WDT			86
#define RK3128_RST_SARADC		87
#define RK3128_RST_DDRPHY		88
#define RK3128_RST_DDRPHY_P		89
#define RK3128_RST_DDRCTRL		90
#define RK3128_RST_DDRCTRL_P		91
#define RK3128_RST_TSP		92
#define RK3128_RST_TSP_CLKIN0		93
#define RK3128_RST_USBHOST0_EHCI		94
#define RK3128_RST_5RES15		95

#define RK3128_RST_HDMI_P		96
#define RK3128_RST_VIO_ARBI_H		97
#define RK3128_RST_VIO_A		98
#define RK3128_RST_VIO_BUS_H		99
#define RK3128_RST_LCDC0_A		100
#define RK3128_RST_LCDC0_H		101
#define RK3128_RST_LCDC0_D		102
#define RK3128_RST_UTMI0		103
#define RK3128_RST_UTMI1		104
#define RK3128_RST_USBPOR		105
#define RK3128_RST_IEP_A		106
#define RK3128_RST_IEP_H		107
#define RK3128_RST_RGA_A		108
#define RK3128_RST_RGA_H		109
#define RK3128_RST_CIF0		110
#define RK3128_RST_PMU		111

#define RK3128_RST_VCODEC_A		112
#define RK3128_RST_VCODEC_H		113
#define RK3128_RST_VIO1_A		114
#define RK3128_RST_HEVC			115
#define RK3128_RST_VCODEC_NIU_A		116
#define RK3128_RST_PMU_NIU		117
#define RK3128_RST_7RES6		118
#define RK3128_RST_LCDC0_S		119
#define RK3128_RST_GPU			120
#define RK3128_RST_7RES9		121
#define RK3128_RST_GPU_NIU_A		122
#define RK3128_RST_EBC_A		123
#define RK3128_RST_EBC_H		124
#define RK3128_RST_7RES13		125
#define RK3128_RST_7RES14		126
#define RK3128_RST_7RES15		127

#define RK3128_RST_CORE_DBG		128
#define RK3128_RST_DBG_P		129
#define RK3128_RST_TIMER0		130
#define RK3128_RST_TIMER1		131
#define RK3128_RST_TIMER2		132
#define RK3128_RST_TIMER3		133
#define RK3128_RST_TIMER4		134
#define RK3128_RST_TIMER5		135
#define RK3128_RST_VIO_H2P		136
#define RK3128_RST_VIO_MIPI_DSI		137
#define RK3128_RST_8RES10		138
#define RK3128_RST_8RES11		139
#define RK3128_RST_8RES12		140
#define RK3128_RST_8RES13		141
#define RK3128_RST_8RES14		142
#define RK3128_RST_8RES15		143

#endif /* _DT_BINDINGS_CLOCK_ROCKCHIP_RK3128_H */
